The invention relates generally to fabrication of a semiconductor device and, more particularly, to a method for fabricating a dual poly gate in a semiconductor device.
A semiconductor device, e.g. a dynamic random access memory (DRAM) device, has a cell region and a peripheral region, and in particular the peripheral region is formed of a complementary metal oxide semiconductor (CMOS). In a general CMOS, a device is formed in a surface structure channel structure in an n-type metal oxide semiconductor (NMOS) region and formed in a buried channel structure in a p-type metal oxide semiconductor (PMOS) region to reduce power consumption of the device and obtain high operation speed. In a buried channel structure, channel length is reduced as the degree of integration of the device is increased and accordingly, there is a problem that a high electric field is applied, which deteriorates leakage current properties. Therefore, a dual poly gate structure is employed to fabricate a p-type MOS transistor having the surface channel structure. In the dual poly gate structure, a p-type poly gate implanted with p-type impurities is placed in a region in which a p-type MOS transistor is formed and an n-type poly gate implanted with n-type impurities is placed in a region in which an n-type MOS transistor is formed.
However, during implementation of a subsequent thermal process for forming a semiconductor device after forming a dual poly gate, there occurs a phenomenon wherein a tungsten silicide (WSix) layer used as a diffusion barrier layer coheres to the structure. In this structure, boron ions doped into an n-type poly gate are diffused out in a direction of a metal layer through a grain boundary of the cohered tungsten silicide layer, resulting in a PMOS defect. Various methods for correcting this phenomenon have been developed, but there occurs a problem that specific resistance of the metal layer used for signal transfer varies with the condition of an underlying layer. Since the variation in the specific resistance of the metal layer by a condition of an underlying layer can influence the overall properties of the semiconductor device, there is required an underlying layer capable of stably maintaining the specific resistance of the metal layer.